An improvement of multi-scale covariance descriptor for embedded system

被引:4
作者
Abid, Nesrine [1 ]
Loukil, Kais [1 ,2 ]
Ouni, Tarek [1 ]
Ayedi, Walid [1 ]
Ammari, Ahmed Chiheb [3 ,4 ]
Abid, Mohamed [1 ,2 ]
机构
[1] Sfax Univ, Natl Sch Engn Sfax, Lab Comp & Embedded Syst, Sfax, Sfax, Tunisia
[2] Sfax Univ, Digital Res Ctr Sfax, Sfax, Sfax, Tunisia
[3] Sultan Qaboos Univ, Fac Engn, Dept Elect & Comp Engn, Muscat, Oman
[4] Carthage Univ, MMA Lab, Natl Inst Appl Sci & Technol, Tunis, Tunisia
关键词
Multi-scale covariance descriptor; Person re-identification; Multi-core architecture; ARM; Embedded system; REGION COVARIANCE; FEATURES; DESIGN; SCALE;
D O I
10.1007/s11554-018-0759-y
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Video surveillance has been a major area of focus for researchers and engineers. Actually, video surveillance includes several useful and complex tasks such as tracking, human detection, re-identification and recognition. Multi-scale covariance (MSCOV) descriptor has recently grown in interest due to its good performances for person detection, re-identification and matching. Unfortunately, its original version requires heavy computations, and it is difficult to be executed in real time on embedded systems. This paper presents two aspects of improvement to adapt the MSCOV descriptor for embedded systems. First, the local binary pattern (LBP) features are introduced and a trade-off between accuracy and processing cost is used to define the best features combination. Second, parallel implementation and embedded co-processor are exploited to accelerate processing time on multi-core CPU architectures. Both optimizations are implemented and evaluated for executing a complete application of person re-identification systems. The software implementation is performed using the VIPeR dataset. Using LBP, 21.57% processing speed-up and 50% less memory requirements for the descriptor computation are achieved without any accuracy performance degradation. We also prototype the proposed design using Zynq platform based on ARM Cortex-A9. The results demonstrate the effectiveness of the parallelization and conduct more than 11 times processing speed-up against the original algorithm.
引用
收藏
页码:419 / 435
页数:17
相关论文
共 37 条
[1]   FPGA-Based Soft-Core Processors for Image Processing Applications [J].
Amiri, Moslem ;
Siddiqui, Fahad Manzoor ;
Kelly, Colm ;
Woods, Roger ;
Rafferty, Karen ;
Bardak, Burak .
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2017, 87 (01) :139-156
[2]   Multiprocessor platform-based design for multimedia [J].
Ammari, A. C. ;
Jemai, A. .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (01) :52-61
[3]  
[Anonymous], CONCURR COMP PRACT E
[4]  
[Anonymous], COMPUT VIS PATTERN R
[5]  
[Anonymous], P 6 INT C COMP VIS C
[6]  
[Anonymous], 2012, P INT C IM PROC COMP
[7]  
[Anonymous], 2012, WORKSH BIOM MEAS SYS
[8]  
[Anonymous], 2015, P INT C PAR PROC APP
[9]  
[Anonymous], 2012, TECHNICAL REPORT
[10]   A fast multi-scale covariance descriptor for object re-identification [J].
Ayedi, Walid ;
Snoussi, Hichem ;
Abid, Mohamed .
PATTERN RECOGNITION LETTERS, 2012, 33 (14) :1902-1907