Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique

被引:27
作者
Gracia, D. [1 ]
Nirmal, D. [1 ]
Moni, D. Jackuline [1 ]
机构
[1] Karunya Inst Technol & Sci, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India
关键词
Gate drain underlap; Tunnel field effect transistor; Double gate; Ambipolar current; Leakage current; FIELD-EFFECT TRANSISTOR; TUNNEL FET; LOW-POWER; HIGH-SPEED; PERFORMANCE; DEVICE; CIRCUIT; OPTIMIZATION; ATTRIBUTES; MODEL;
D O I
10.1016/j.aeue.2018.09.024
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, a dual metal (DM) double-gate (DG) Tunnel Field Effect Transistor (DMDG-TFET) with drain gate underlap is proposed to overcome the challenges in conventional TFET. The ON-current (I-on), OFF current (I-off), I-on/I-off ratio, subthreshold swing (SS) and ambipolar current (I-ambi) of the proposed device with drain underlap are investigated as gate length is scaled (L-GATE) down. The proposed device gives a better suppression in leakage current and low ambipolar current. The suppressed leakage current (loft) and ambipolar current (I-ambi) are 9.49 x 10 14 A/pm and 1.95 x 10 12 A/pm respectively for a gate length (L-GATE) of 36 nm and a channel length (Lb) of 50 nm for a supply voltage of 0.5 V. Excellent switching behavior is achieved when gate length (L-GATE) is 72% of the channel length (L-ch). The proposed architecture is suitable for low power applications. (C) 2018 Elsevier GmbH. All rights reserved.
引用
收藏
页码:164 / 169
页数:6
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