Compact Wideband Equivalent-Circuit Model for Electrical Modeling of Through-Silicon Via

被引：64

作者：

Liu, En-Xiao ^{[1
]}

Li, Er-Ping ^{[1
]}

Ewe, Wei-Bin ^{[1
]}

Lee, Hui Min ^{[1
]}

Lim, Teck Guan ^{[2
]}

Gao, Shan ^{[2
]}

机构：

[1] ASTAR, Inst High Performance Comp, Elect & Photon Dept, RF Engn Grp, Singapore, Singapore

[2] ASTAR, Microsyst Modules & Components MMC Lab, Inst Microelect, Singapore, Singapore

来源：

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | 2011年 / 59卷 / 06期

关键词：

Compact wideband equivalent-circuit model; Fourier-Bessel expansion; 3-D integrated circuits (ICs) and packaging; through-silicon via (TSV);

D O I：

10.1109/TMTT.2011.2116039

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a compact wideband equivalent-circuit model for electrical modeling of through-silicon vias (TSVs) in 3-D stacked integrated circuits and packaging. Rigorous closed-form formulas for the resistance and inductance of TSVs are derived from the magneto-quasi-static theory with a Fourier-Bessel expansion approach, whereas analytical formulas from static solutions are used to compute the capacitance and conductance. The equivalent-circuit model can capture the important parasitic effects of TSVs, including the skin effect, proximity effect, lossy effect of silicon, and semiconductor effect. Therefore, it yields accurate results comparable to those with 3-D full-wave solvers.

引用

页码：1454 / 1460

页数：7

共 14 条

[1]

[Anonymous], 2007, MOSFET Modeling for VLSI Simulation: Theory and Practice

[2]

Ansoft HFSS, 2009, ANS HFSS

[3]

Bandyopadhyay T., 2009, P IEEE INT C 3D SYST, P1

[4] Wave propagation over parllel wires - The proximity effect [J].

Carson, JR .

PHILOSOPHICAL MAGAZINE, 1921, 41 (244) :607-633

[5] Frequency-dependent crosstalk simulation for on-chip interconnections [J].

Deutsch, A ;

Smith, HH ;

Surovic, CW ;

Kopcsay, GV ;

Webber, DA ;

Coteus, PW ;

Katopis, GA ;

Becker, WD ;

Dansky, AH ;

Sai-Halasz, GA ;

Restle, PJ .

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 1999, 22 (03) :292-308

[6] Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].

Knickerbocker, JU ;

Andry, PS ;

Buchwalter, LP ;

Deutsch, A ;

Horton, RR ;

Jenkins, KA ;

Kwark, YH ;

McVicker, G ;

Patel, CS ;

Polastre, RJ ;

Schuster, C ;

Sharma, A ;

Sri-Jayantha, SM ;

Surovic, CW ;

Tsang, CK ;

Webb, BC ;

Wright, SL ;

McKnight, SR ;

Sprogis, EJ ;

Dang, B .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753

[7] Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects [J].

Li, Er-Ping ;

Wei, Xing-Chang ;

Cangellaris, Andreas C. ;

Liu, En-Xiao ;

Zhang, Yao-Jiang ;

D'Amore, Marcello ;

Kim, Joungho ;

Sudo, Toshio .

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2010, 52 (02) :248-265

[8] Novel Methods for Modeling of Multiple Vias in Multilayered Parallel-Plate Structures [J].

Liu, En-Xiao ;

Li, Er-Ping ;

Oo, Zaw Zaw ;

Wei, Xingchang ;

Zhang, Yaojiang ;

Vahldieck, Ruediger .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2009, 57 (07) :1724-1733

[9]

PLAS GVD, 2010, P INT SOL STAT CIRC, P148

[10] CHARACTERIZATION OF VIA CONNECTIONS IN SILICON CIRCUIT BOARDS [J].

QUINE, JP ;

WEBSTER, HF ;

GLASCOCK, HH ;

CARLSON, RO .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1988, 36 (01) :21-27

← 1 2 →