A FAULT-TOLERANT LAYER FOR DYNAMICALLY RECONFIGURABLE MULTI-PROCESSOR SYSTEM-ON-CHIP

Parallel computing is an important trend of embedded system. One possible response to increasing requirements in computational power is to distribute tasks over various processors and let these processors operate in parallel. Soft-core processors and FPGAs require low Non-Recurring Engineering costs to develop such multi-processors systems. Furthermore, certain FPGAs allow dynamic partial run-time reconfiguration, but their high sensitivity to electronic defects can cause the system disfunction. This paper presents a fault-tolerant multi-processor system-on-chip based on the dynamic reconfiguration of the entire platform. Also, a modification of the standard methodology of the run-time self-reconfiguration, who facilitates the complex modular concept design, is presented in this paper.