A scalable shared buffer ATM switch embedded SPRAMS

被引：0

作者：

Jeong, GJ ^{[1
]}

Shim, JW ^{[1
]}

Lee, MK ^{[1
]}

Ahn, SH ^{[1
]}

机构：

[1] Yonsei Univ, Dept EE, Seoul 120749, South Korea

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes the architecture of a scalable shared buffer ATM switch and VLSI implementation. It provides scalability in port size and buffer size. The prototype chip has been designed for 4 x 4 ATM switch which has a shared buffer for 128 ATM cells. It is integrated in 0.6 mu m twin well, double-metal, and single-poly CMOS technology. Operating frequency is 80MHz. Core size is 11 x 10mm(2). It supports 622Mbps per port.

引用

页码：A109 / A112

页数：4