Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

被引：46

作者：

Heo, Sunwoo ^{[1
]}

Kim, Sunmean ^{[2
]}

Kim, Kiyung ^{[1
]}

Lee, Hyeji ^{[1
]}

Kim, So-Young ^{[1
]}

Kim, Yun Ji ^{[1
]}

Kim, Seung Mo ^{[1
]}

Lee, Ho-In ^{[1
]}

Lee, Segi ^{[2
]}

Kim, Kyung Rok ^{[2
]}

Kang, Seokhyeong ^{[3
]}

Lee, Byoung Hun ^{[1
]}

机构：

[1] Gwangju Inst Sci & Technol, Sch Mat Sci & Engn, Ctr Emerging Elect Devices & Syst, Gwangju 61005, South Korea

[2] Ulsan Natl Inst Sci & Technol, Dept Elect Engn, Ulsan 44919, South Korea

[3] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 37673, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2018年 / 39卷 / 12期

基金：

新加坡国家研究基金会;

关键词：

Graphene barristor; ternary full adder; multi threshold voltage ternary graphene barristor; ternary logic; FIELD-EFFECT TRANSISTOR; DEVICE; DESIGN;

D O I：

10.1109/LED.2018.2874055

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of similar to 10(-16) J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-V-th ternary graphene barristors.

引用

页码：1948 / 1951

页数：4

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