On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments

被引:45
作者
Radojkovic, Petar [1 ]
Girbal, Sylvain
Grasset, Arnaud
Quinones, Eduardo [1 ]
Yehia, Sami
Cazorla, Francisco J. [1 ]
机构
[1] Barcelona Supercomp Ctr, Barcelona 08034, Spain
关键词
Measurement; Multithreaded COTS processors; Resource-stressing benchmarks; WCET; evaluation;
D O I
10.1145/2086696.2086713
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Commercial Off-The-Shelf (COTS) processors are now commonly used in real-time embedded systems. The characteristics of these processors fulfill system requirements in terms of time-to-market, low cost, and high performance-per-watt ratio. However, multithreaded (MT) processors are still not widely used in real-time systems because the timing analysis is too complex. In MT processors, simultaneously-running tasks share and compete for processor resources, so the timing analysis has to estimate the possible impact that the inter-task interferences have on the execution time of the applications. In this paper, we propose a method that quantifies the slowdown that simultaneously-running tasks may experience due to collision in shared processor resources. To that end, we designed benchmarks that stress specific processor resources and we used them to (1) estimate the upper limit of a slowdown that simultaneously-running tasks may experience because of collision in different shared processor resources, and (2) quantify the sensitivity of time-critical applications to collision in these resources. We used the presented method to determine if a given MT processor is a good candidate for systems with timing requirements. We also present a case study in which the method is used to analyze three multithreaded architectures exhibiting different configurations of resource sharing. Finally, we show that measuring the slowdown that real applications experience when simultaneously-running with resource-stressing benchmarks is an important step in measurement-based timing analysis. This information is a base for incremental verification of MT COTS architectures.
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页数:25
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