A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process

被引：0

作者：

Lee, Chia-Hsin ^{[1
,2
]}

Hou, Chih-Huei ^{[1
]}

Huang, Chun-Po ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

Hsich, Yuan-Ta ^{[2
]}

Juang, Ying-Zong ^{[2
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, 95504,5E,Chi Mei Bldg,Tzu Chiang Campus, Tainan, Taiwan

[2] Natl Chip Implementat Ctr, 7F,26,Prosper Rd 1,Sci Pk, Hsinchu, Taiwan

来源：

2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2016年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

引用

页数：4

共 9 条

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