Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

被引：0

作者：

Barraud, S. ^{[1
,2
]}

Previtali, B. ^{[1
,2
]}

Lapras, V. ^{[1
,2
]}

Vizioz, C. ^{[1
,2
]}

Hartmann, J. -M. ^{[1
,2
]}

Martinie, S. ^{[1
,2
]}

Lacord, J. ^{[1
,2
]}

Casse, M. ^{[1
,2
]}

Dourthe, L. ^{[1
,2
]}

Loup, V. ^{[1
,2
]}

Romano, G. ^{[3
]}

Rambal, N. ^{[1
,2
]}

Chalupa, Z. ^{[1
,2
]}

Bernier, N. ^{[1
,2
]}

Audoit, G. ^{[1
,2
]}

Jannaud, A. ^{[4
]}

Delaye, V. ^{[1
,2
]}

Balan, V. ^{[1
,2
]}

Rozeau, O. ^{[1
,2
]}

Ernst, T. ^{[1
,2
]}

Vinet, M. ^{[1
,2
]}

机构：

[1] CEA, LETI, Minatec Campus, F-38054 Grenoble, France

[2] Univ Grenoble Alpes, Minatec Campus, F-38054 Grenoble, France

[3] STMicroelectronics, F-38926 Crolles, France

[4] SERMA Technol, Minatec Campus, F-38054 Grenoble, France

来源：

2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high-kappa metal gate process and self-aligned-contacts. Back biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

引用

页数：4

共 17 条

[1] Bardon M. Garcia, 2018, VLSI
[2] Barraud S., 2017, VLSI
[3] Barraud S., 2016, VLSI, DOI [10.1109/IEDM.2016.7838441, DOI 10.1109/VLST.2016.7838441]
[4] Bera L. K., 2006, VLSI, DOI [10.1109/IEDM.2006.346841, DOI 10.1109/VLST.2006.346841]
[5] Bernard E., 2008, VLSI TECH S, P16
[6] Combining 2 nm Spatial Resolution and 0.02% Precision for Deformation Mapping of Semiconductor Specimens in a Transmission Electron Microscope by Precession Electron Diffraction
Cooper, David
Bernier, Nicolas
Rouviere, Jean-Luc
[J]. NANO LETTERS, 2015, 15 (08) : 5289 - 5294
[7] Dupre C., 2008, VLSI, DOI [10.1109/IEDM.2008.4796805, DOI 10.1109/VLST.2008.4796805]
[8] Ernst T., 2006, VLSI, DOI [10.1109/IEDM.2006.346955, DOI 10.1109/VLST.2006.346955]
[9] Hartmann J. M., 2017, SEMICOND SCI TECH, V32
[10] Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices
Lacord, J.
Martinie, S.
Rozeau, O.
Jaud, M. -A.
Barraud, S.
Barbe, J. C.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (02) : 781 - 786

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