Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

被引：6

作者：

Bahoura, Mohammed ^{[1
]}

机构：

[1] Univ Quebec, Dept Engn, 300 Allee Ursulines, Rimouski, PQ G5L 3A1, Canada

来源：

ELECTRONICS | 2017年 / 6卷 / 04期

基金：

加拿大自然科学与工程研究理事会;

关键词：

FPGA; hardware/software co-simulation; pipelining; speech enhancement; multi-band spectral subtraction; signal-to-noise ratio; FPGA IMPLEMENTATION; ENHANCING SPEECH; COLORED NOISE; SUPPRESSION; BEARINGS;

D O I：

10.3390/electronics6040073

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device.

引用

页数：12

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