High-efficiency control structure for CMOS flash memory charge pumps

被引：6

作者：

Boffino, C ^{[1
]}

Cabrini, A ^{[1
]}

Khouri, O ^{[1
]}

Torelli, G ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/ISCAS.2005.1464539

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A basic drawback of charge pump circuits is represented by undesired power losses, that must be reduced as much as possible in particular for portable applications. This paper presents a control structure conceived to reduce the power consumption of voltage elevators based on Dickson topology. To evaluate the effectiveness of the proposed control scheme, a new definition of power efficiency is introduced. The presented solution provides an effective power management, thus ensuring an efficiency improvement of about 40% during stand-by.

引用

页码：121 / 124

页数：4

共 4 条

[1] ON-CHIP HIGH-VOLTAGE GENERATION IN MNOS INTEGRATED-CIRCUITS USING AN IMPROVED VOLTAGE MULTIPLIER TECHNIQUE [J].