Damascene test structures for the evaluation of barrier layer performance against copper diffusion

被引:6
作者
Motte, P
Swaanen, M
Torres, J
Gilet, JM
Wyborn, G
机构
[1] STMicroelect, F-38926 Crolles, France
[2] France Telecom, Bagneux, France
关键词
diffusion barrier; copper; CVD-TiN; IMP-TaN; barrier performance test; etch-pit;
D O I
10.1016/S0167-9317(00)00459-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Both IMP TaN and CVD TiN barriers have been shown to be excellent materials against copper diffusion using etch-pit, bias-thermal-stress (BTS) or C(V) tests on planar structures. These results however cannot account for the real barrier thickness and stoichiometry when deposited in damascene features. Such information is critical for advanced technologies exploiting high aspect ratio design rules. Via structures, 0.32 and 0.26 mum in diameter and 1 mum deep, etched through SiO2 down to hare silicon, are combined with a standard etch-pit test to look for the formation of copper silicide as a function of barrier material and process conditions. Using these test-structures it was shown that the CVD process would be mandatory to maintain the required copper barrier performance in sub-quarter micron technology. (C) 2001 Elsevier Science BN. All rights reserved.
引用
收藏
页码:291 / 296
页数:6
相关论文
共 2 条
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CHOE MS, 1999, P IITC, P62
[2]  
MARCADEL C, 1997, P IEEE IEDM, P405