DeSpErate plus plus : An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling

被引:9
|
作者
Mariani, Giovanni [1 ]
Palermo, Gianluca [1 ]
Zaccaria, Vittorio [1 ]
Silvano, Cristina [1 ]
机构
[1] Politecn Milan, Dipartimento Elettron Informaz & Bioingn, I-20133 Milan, Italy
关键词
Computer performance; concurrency control; design automation; evolutionary computation; high performance computing; parallel architectures; SYSTEM-LEVEL DESIGN; OPTIMIZATION; ALGORITHM; ACCURATE;
D O I
10.1109/TCAD.2014.2379634
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26x to 4x with respect to other parallel state-of-the art DSE techniques.
引用
收藏
页码:293 / 306
页数:14
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