A Design of low power Adders

被引：0
|
作者：
Priya, S. Sridevi Sathya [2 ]
Raju, Benita Poul [1 ]
Benita, B.
Dharani
机构：
[1] Karunya Inst Technol, Dept Elect Technol, Coimbatore, Tamil Nadu, India
[2] Karunya Univ, Dept Elect Technol, Coimbatore, Tamil Nadu, India
来源：
2018 4TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) | 2018年
关键词：
low power adder; adder; Carry generators; power consumption; multiplexers;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The low power adder is designed in this paper using Carry-Select Modified-Tree(CSMT) adder for fast carry generation and for binary addition. The results are analyzed and the performances are compared. This adder makes the use of multiplexers.The greatest advantage of this adder is that it uses very few multiplexers and consumes least amount of energy for specified latency. Cany-select addition is used in the architecture. The adder is implemented using Multiplexer block and longer carry-select adders are be replaced by modified tree structure to maintain the multiplexer complexity. The CSMT architecture in adder can reduce the multiplexer complexity.By using this concept the 38% power is reduced when compared to the conventional adder.
引用
收藏
页码：245 / 249
页数：5
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