Optimization of 5V power devices based on CMOS for hot-carrier degradation

被引：0

作者：

Nakamura, K ^{[1
]}

Naka, T ^{[1
]}

Matsushita, K ^{[1
]}

Matsudai, T ^{[1
]}

Yasuhara, N ^{[1
]}

Endo, K ^{[1
]}

Suzuki, F ^{[1
]}

Nakagawa, A ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Discrete Semicond Div, Saiwai Ku, Kawasaki, Kanagawa 2128583, Japan

来源：

PROCEEDINGS OF THE 17TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose "power CMOS," suitable for use as large current output devices. The proposed structure can be fabricated by low cost 0.6um logic CMOS process and assures long-term reliability even under the stress of hot-electrons. The developed power CMOS have achieved low specific on resistances of 8.1m Omega mm(2) for NMOS and 21.1 m Omega mm(2) for PMOS.

引用

页码：335 / 338

页数：4

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