Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs

被引：16

作者：

Gebhardt, Daniel ^{[1
]}

You, Junbok ^{[2
]}

Stevens, Kenneth S. ^{[3
]}

机构：

[1] Univ Utah, Sch Comp, Salt Lake City, UT 84111 USA

[2] Texas Instruments Inc, Dallas, TX 75243 USA

[3] Univ Utah, Dept Elect & Comp Engn, Salt Lake City, UT 84111 USA

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2011年 / 30卷 / 09期

基金：

美国国家科学基金会;

关键词：

Application-specific; asynchronous design; embedded; GALS; low-power; network-on-chip; system-on-chip; ON-CHIP; NETWORK; INTERCONNECT;

D O I：

10.1109/TCAD.2011.2149870

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The energy usage of on-chip interconnects is a concern for many system-on-chips targeting portable battery-powered devices. We have designed and evaluated a network-on-chip (NoC) for such an application, including tools to optimize for power and communication latency. Our asynchronous (clockless) network operates with efficient two-phase bundled-data links and four-phase routers. The topology and router floorplan is determined by our tool, ANetGen, which optimizes the network for energy and latency using simulated annealing and force-directed placement methods. We compare our solutions against a traditional synchronous NoC as specified by the COSI-2.0 framework and ORION 2.0 router and wire energy models. Traffic is simulated with SystemC functional models, and messages are generated with a "bursty" self-similar b-model. Results indicate our asynchronous network was more energy-efficient, lower in area, and provided comparable or superior message latency.

引用

页码：1387 / 1399

页数：13

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