A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem

被引：0

作者：

Lee, Jung-Ho ^{[1
]}

Yoon, Sung-Rok ^{[1
]}

Pyun, Kwang-Eui ^{[1
]}

Park, Sin-Chong ^{[1
]}

机构：

[1] Informat & Commun Univ, Taejon 305732, South Korea

来源：

2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2008年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Since 2001, there have been a myriad of papers on systematic analysis of Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC). Nevertheless, we only have a few of their practical application. Till now, main interest of researchers has been to adapt NoC to the communication intensive multimedia system like H.263. However, this paper attempts to expand the domain of NoC platform to one of the wireless security algorithms (TKIP), because its inter-component transaction pattern shows considerable characteristic for NoC. This paper consists of the explanation on operational sequence of the algorithm in chosen architecture and the brief illustration of important composing NoC blocks (Network Interface, Router).

引用

页码：567 / 570

页数：4

共 30 条

[1] Some Remarks on the TKIP Key Mixing Function of IEEE 802.11i
韩玮
郑东
陈克非
Journal of Shanghai Jiaotong University(Science), 2009, 14 (01) : 81 - 85
[2] Some remarks on the TKIP key mixing function of IEEE 802.11i
Han W.
Zheng D.
Chen K.-F.
Journal of Shanghai Jiaotong University (Science), 2009, 14 (1) : 81 - 85
[3] A Practical Cryptographic Denial of Service Attack against 802.11i TKIP and CCMP
Eian, Martin
CRYPTOLOGY AND NETWORK SECURITY, 2010, 6467 : 62 - 75
[4] A multi-processor platform for signal processing
Freeman, BJ
SIGNAL PROCESSING, SENSOR FUSION, AND TARGET RECOGNITION VII, 1998, 3374 : 483 - 494
[5] Efficient low-latency RC4 architecture designs for IEEE 802.11i WEP/TKIP
Lee, Jun-Dian
Fan, Chih-Peng
2007 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS, VOLS 1 AND 2, 2007, : 64 - +
[6] Hardware Transactional Memory on Multi-processor FPGA Platform
Sirkunan, Jeevan
Ooi, Chia Yee
Shaikh-Husin, N.
Hau, Yuan Wen
Marsono, M. N.
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 2744 - 2747
[7] A Scalable Bootloader and Debugger Design for An NoC-based Multi-processor SoC
Hartono, Dicky
Ng, M. S.
Lim, Z. N.
Lee, S. W.
Yap, V. V.
Tang, C. M.
2015 3RD INTERNATIONAL CONFERENCE ON NEW MEDIA STUDIES (CONMEDIA), 2015,
[8] Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management
Paulin, PG
Pilkington, C
Langevin, M
INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 48 - 53
[9] Architecture for multi-processor SoC platform using dedicated channels
Lee, G
Park, SC
Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, 2005, : 525 - 529
[10] Transaction level modeling of NoC based multi-processor architecture for wireless communication system
Yoon, Sung-Rok
Park, Sin-Chong
2006 ASIA-PACIFIC CONFERENCE ON COMMUNICATION, VOLS 1 AND 2, 2006, : 694 - 697

← 1 2 3 →