Research challenges for on-chip interconnection networks

被引：270

作者：

Owens, John D. ^{[1
]}

Dally, William J.

Ho, Ron

Jayasimha, D. N.

Keckler, Stephen W.

Peh, Li-Shiuan

机构：

[1] Univ Calif Davis, Davis, CA 95616 USA

[2] Stanford Univ, Dept Comp Sci, Stanford, CA 94305 USA

[3] Sun Microsyst Inc, Menlo Pk, CA USA

[4] Univ Texas, Austin, TX 78712 USA

来源：

IEEE MICRO | 2007年 / 27卷 / 05期

基金：

美国国家科学基金会;

关键词：

Embedded systems; Interconnection networks; Multicore architectures; Network on chip; On-chip interconnection networks; System on chip;

D O I：

10.1109/MM.2007.4378787

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

On-chip interconnection networks are rapidly becoming a key enabling technology for commodity multicore processors and SOCs common in consumer embedded systems. Last year, The National Science Foundation initiated a workshop that addressed upcoming research issues in OCIN technology, design, and implementation and set a direction for researchers in the field.

引用

页码：96 / 108

页数：13

共 16 条

[1] [Anonymous], FEW CORES MANY TERA
[2] Networks on chips: A new SoC paradigm
Benini, L
De Micheli, G
[J]. COMPUTER, 2002, 35 (01) : 70 - +
[3] BERGMAN K, 2006, WORKSH ON OFF CHIP I
[4] BREWER EA, 1995, P 7 ACM S PAR ALG AR, P42
[5] Dally WJ, 2001, DES AUT CON, P684, DOI 10.1109/DAC.2001.935594
[6] THE MESSAGE-DRIVEN PROCESSOR - A MULTICOMPUTER PROCESSING NODE WITH EFFICIENT MECHANISMS
DALLY, WJ
FISKE, JAS
KEEN, JS
LETHIN, RA
NOAKES, MD
NUTH, PR
DAVISON, RE
FYLER, GA
[J]. IEEE MICRO, 1992, 12 (02) : 23 - 39
[7] Part I: A theory for deadlock-free dynamic network reconfiguration
Duato, J
Lysne, O
Pang, RM
Pinkston, TM
[J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2005, 16 (05) : 412 - 427
[8] Eisley N, 2006, INT SYMP MICROARCH, P321
[9] Gratz P, 2007, NOCS 2007: FIRST INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS, P7
[10] Grecu C., 2007, INITIATIVE OPEN NETW

← 1 2 →