Effect of the interfacial (low-k SiO2 vs high-k Al2O3) dielectrics on the electrical performance of a-ITZO TFT

被引:24
作者
Taouririt, Taki Eddine [1 ]
Meftah, Afak [1 ]
Sengouga, Nouredine [1 ]
机构
[1] Univ Biskra, Lab Metall & Semiconducting Mat, BP 145, Biskra 07000, Algeria
关键词
A-ITZO; SiO2; Al2O3; TFT; High-k; EOT; Silvaco Atlas; ATOMIC LAYER DEPOSITION; THIN; SILICON; FILMS;
D O I
10.1007/s13204-018-0866-x
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
In this work, the effect of an interfacial low-k dielectric layer such as -SiO2 was suggested along with the effect of an interfacial high-k dielectric layer such as -Al2O3 on the electrical characteristics and then the electrical properties of the a-ITZO TFT such as the equivalent oxide thickness (EOT) of gate dielectric, gate capacitance per unit area (C-i), on-current (I-on), on-off current (I-on/I-off) ratio and field-effect mobility (mu(FE)) of the a-ITZO TFT. The main purpose of this study is to conduct a comparative study to highlight the impact of the interfacial high-k dielectrics such as -Al2O3, compared to low-k -SiO2, the existing between the a-ITZO active layer and high-k -Hfv layer in a-ITZO TFT based on the double-layered dielectric. Therefore, the several analyses were implemented through numerical simulation of the device by the Silvaco TCAD Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between different types of the interfacial (low-k and high-k) dielectric oxides and the performance of a-ITZO TFT. The results showed that TFT based on the double-layered dielectric -(Al2O3/HfO2) with a physical thickness (PT = 30 nm) it can provide good electrical properties (EOT = 6.33 nm, C-i = 5.45 x 10(-7) F cm(-2), I-on = 1.61 x 10(-5) A, I-on/I-off = 1.56 x 10(9) and mu(FE) = 24.11 cm(2) V-1 s(-1)) better than the properties provided by TFT based on the double-layered dielectric -(SiO2/HfO2) for the same physical thickness (EOT = 12.23 nm, C-i = 2.82 x 10(-7) F cm(-2), I-on = 8.54 x 10(-6) A, I-on/I-off = 8.27 x 10(8) and m(-2) = 29.31 cm(2) V-1 s(-1)). However, we cannot neglect the fundamental role of the interfacial low-k -SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. In addition, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.
引用
收藏
页码:1865 / 1875
页数:11
相关论文
共 42 条
[1]   Numerical simulation of bias and photo stress on indium-gallium-zinc-oxide thin film transistors [J].
Adaika, M. ;
Meftah, Af. ;
Sengouga, N. ;
Henini, M. .
VACUUM, 2015, 120 :59-67
[2]  
Afanasev V. V., 2008, INT PHOT SPECTR
[3]   Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? [J].
Ando, Takashi .
MATERIALS, 2012, 5 (03) :478-500
[4]  
[Anonymous], 2014, ATLAS US MAN DEV SIM
[5]   Photoelectron emission microscopy of ultrathin oxide covered devices [J].
Ballarotto, VW ;
Breban, M ;
Siegrist, K ;
Phaneuf, RJ ;
Williams, ED .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2002, 20 (06) :2514-2518
[6]  
Chagarov EA, 2010, FUNDAMENTALS OF III-V SEMICONDUCTOR MOSFETS, P93, DOI 10.1007/978-1-4419-1547-4_5
[7]  
Chhowalla M, 2016, NAT REV MATER, V1, DOI [10.1038/natrevmats.2016.52, 10.1038/natrevmats2016.52]
[8]   TRANSCONDUCTANCE OF SILICON-ON-INSULATOR (SOI) MOSFETS [J].
COLINGE, JP .
IEEE ELECTRON DEVICE LETTERS, 1985, 6 (11) :573-574
[9]  
Colombo L, 2007, ELECTROCHEM SOC INTE, V16, P51
[10]  
Dass D, 2013, J NANO ELECT PHYS, V5, P1