Threshold voltage (V-T) and mobility (mu) shifts due to process related variability and Negative Bias Temperature Instability are experimentally characterized in pMOSFETs. A simulation technique to include the time-dependent variabilities of V-T and mu in circuit simulators is presented and used to evaluate their effects on CMOS inverters performance. The results show that mobility degradation under NBTI stresses could have to be considered for the evaluation of the circuit performance after device aging. (C) 2011 Elsevier B.V. All rights reserved.
引用
收藏
页码:1384 / 1387
页数:4
相关论文
共 12 条
[1]
[Anonymous], 2008, Proc. of 46th IRPS, DOI DOI 10.1109/RELPHY.2008.4558858