A 0.3V, 12nW, 47 f J/conv, Fully Digital Capacitive Sensor Interface in 0.18μm CMOS

被引:0
|
作者
Savaliya, Ankit [1 ]
Mishra, Biswajit [1 ]
机构
[1] DA IICT, VLSI & Embedded Res Lab, Gandhinagar 382007, India
来源
2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA) | 2015年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a fully-digital ultra low power capacitive sensor interface, which directly converts sensor capacitance to its digital value. Capacitive sensor interface is divided into two parts, 1) Capacitance to time converter (CTC) and 2) time to digital converter (TDC). The proposed design demonstrates the working principle of CTC and TDC and its implementation using UMC 0.18 mu m CMOS technology. Demonstration of CTC through capacitive controlled oscillator (CCO) is carried out by keeping sensor capacitance in the range of 5pF - 25pF. CCO generates pulse signals according to sensor capacitance and feeds it to the TDC. TDC consists of a delay line, edge combiner and counter and measures pulse width of pulse signals generated from CCO and gives their digital equivalent value in two forms:- fine timing data and coarse timing data. Finally, control logic unit is implemented to control each unit and to reduce power consumption of TDC design. The power consumption of the proposed interface is 12nW, acquisition time 528 mu S, peak FOM of 47 f J/conv with 6.1 ENOB at an operating voltage of 0.3V.
引用
收藏
页数:6
相关论文
empty
未找到相关数据