A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems

被引：0

作者：

Wu, Yimin ^{[1
]}

Lan, Jingchao ^{[1
]}

Chen, Min ^{[1
]}

Ye, Fan ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

来源：

APCCAS 2020: PROCEEDINGS OF THE 2020 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2020) | 2020年

关键词：

Ultrasound Imaging; Pipelined-SAR; ADC; Stage Resolution; Optimization;

D O I：

10.1109/apccas50809.2020.9301652

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a 16-channel 14bit 50MS/s ADC designed with a 0.18 mu m process, used in integrated ultrasound imaging systems. The design considerations of stage resolution distribution are thoroughly discussed. The optimal stage resolution for a 14bit pipelined-SAR is "5-5-6", achieving the best power and area efficiency. According to this, the prototype chip is designed with complete peripheral circuits including LVDS, SPI, bandgap, etc. The measurement results show that this compact design features the highest resolution and SNDR among recent designs with a competitive FoM.

引用

页码：3 / 6

页数：4