A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems

被引：0

作者：

Wu, Yimin ^{[1
]}

Lan, Jingchao ^{[1
]}

Chen, Min ^{[1
]}

Ye, Fan ^{[1
]}

Ren, Junyan ^{[1
]}

机构：

[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 201203, Peoples R China

来源：

APCCAS 2020: PROCEEDINGS OF THE 2020 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2020) | 2020年

关键词：

Ultrasound Imaging; Pipelined-SAR; ADC; Stage Resolution; Optimization;

D O I：

10.1109/apccas50809.2020.9301652

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a 16-channel 14bit 50MS/s ADC designed with a 0.18 mu m process, used in integrated ultrasound imaging systems. The design considerations of stage resolution distribution are thoroughly discussed. The optimal stage resolution for a 14bit pipelined-SAR is "5-5-6", achieving the best power and area efficiency. According to this, the prototype chip is designed with complete peripheral circuits including LVDS, SPI, bandgap, etc. The measurement results show that this compact design features the highest resolution and SNDR among recent designs with a competitive FoM.

引用

页码：3 / 6

页数：4

共 50 条

[1] A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier
Chu, Honghao
Li, Fule
2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2017, : 628 - 631
[2] A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution
Wu, Yimin
Ye, Fan
Ren, Junyan
ELECTRONICS, 2022, 11 (05)
[3] Systematic Design of 10-bit 50MS/s Pipelined ADC
Zhu, Kehan
Balagopal, Sakkarapani
Saxena, Vishal
2013 IEEE WORKSHOP ON MICROELECTRONICS AND ELECTRON DEVICES (WMED), 2013, : 17 - 20
[4] Design of a 10 bit 50MS/s SAR ADC in 14nm SOI FinFET CMOS
Wang, Aili
Wang, Yu
Dhawan, Vandana
Shi, Richard
2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2015, : 85 - 86
[5] A Study of a10-bit 50MS/s Low Voltage Low Power Pipelined ADC
Zhang, Cuncai
Wang, Hui
Cheng, Yuhua
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1972 - 1975
[6] A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC
Wu, Chao
Yuan, Jie
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (05) : 1446 - 1454
[7] An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC
Xi, Yin-Zheng
Yang, Wei-Ping
Li, Nan
Diao, Jie-Tao
Zhang, Sheng-Kun
Ding, Hao
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 179
[8] A Novel Self-Calibration Scheme for 12-bit 50MS/s SAR ADC
Jung, In-Seok
Kim, Yong-Bin
2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2014, : 5 - 8
[9] A Fast-Convergence and Robust Digital Calibration Algorithm for a 14-bit 200-MS/s Hybrid Pipelined-SAR ADC
Qing, Shan
Li, Guang-Jun
Li, Qiang
2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2012, : 442 - 445
[10] A 9-bit 50MS/s Asynchronous SAR ADC in 28nm CMOS
Cao, Tuan-Vu
Aunet, Snorre
Ytterdal, Trond
2012 NORCHIP, 2012,

← 1 2 3 4 5 →