FPGA implementation of digital filters synthesized using the FRM technique

被引：0
作者：
Lim, YC [1 ]
Yu, YJ
Zheng, HQ
Foo, SW
机构：
[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore 119260, Singapore
[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
来源：
CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2003年 / 22卷 / 02期
关键词：
digital filters; FIR filters; FRM technique;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The effective length of a filter designed using the frequency-response masking (FRM) technique is very long and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the field programmable gate array (FPGA) and external memory when the random logic is implemented using the FPGA and the delay elements are implemented using an external memory such as dynamic random access memory.
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页码：211 / 218
页数：8
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