Selective restart of threads for efficient thread-level speculation on multicore architecture

被引:0
作者
Lee, Sungjae [1 ]
Lee, Inhwan [1 ]
机构
[1] Hanyang Univ, Sch Elect & Comp Engn, Seoul 133791, South Korea
关键词
multicore architecture; thread-level speculation; selective restart;
D O I
10.1587/elex.9.290
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An efficient recovery method for thread-level speculation (TLS) is proposed. The method tracks the inter-thread data dependence as a method for identifying those threads that are obviously unaffected by a data dependence violation. The method is simple to implement. Still, the simulation results using benchmark applications show that the method can significantly reduce the number of unnecessary thread restarts and consequently improve the performance of TLS. Specifically, when compared with the baseline TLS, TLS with the proposed method is 2.3 times faster for IS, 1.7 times faster for equake, and 3.5 times faster for mcf with the use of 64 cores. With the method, the performance of TLS increases steadily up to 64 cores for IS, equake, and mcf, while the speedup of the baseline TLS starts to saturate at 8 or 16 cores.
引用
收藏
页码:290 / 295
页数:6
相关论文
共 5 条
[1]  
HAMMOND L, 1998, P 8 INT C ARCH SUPP, P58
[2]   A chip-multiprocessor architecture with speculative multithreading [J].
Krishnan, V ;
Torrellas, J .
IEEE TRANSACTIONS ON COMPUTERS, 1999, 48 (09) :866-880
[3]  
Prabhu M.K., 2005, PPOPP 05, P142
[4]  
Renau J., 2005, PROC INT C SUPERCOMP, P179, DOI DOI 10.1145/1088149.1088173
[5]   The potential for using thread-level data speculation to facilitate automatic parallelization [J].
Steffan, JG ;
Mowry, TC .
1998 FOURTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 1998, :2-13