共 27 条
Tuning the hysteresis voltage in 2D multilayer MoS2 FETs
被引:30
作者:

Jiang, Jie
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Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China

Zheng, Zhouming
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Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China

Guo, Junjie
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Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China
机构:
[1] Cent S Univ, Sch Phys & Elect, Hunan Key Lab Super Microstruct & Ultrafast Proc, Changsha 410083, Hunan, Peoples R China
基金:
中国国家自然科学基金;
关键词:
MoS2;
Two-dimensional materials;
Hysteresis voltage;
Traps;
Field-effect transistors;
LAYER MOS2;
ZIGZAG GRAPHENE;
MONOLAYER MOS2;
TRANSISTORS;
HETEROJUNCTION;
D O I:
10.1016/j.physb.2016.06.025
中图分类号:
O469 [凝聚态物理学];
学科分类号:
070205 ;
摘要:
The hysteresis tuning is of great significance before the two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistors (FETs) can be practically used in the next-generation nanoelectronic devices. In this paper, a simple and effective annealing method was developed to tune the hysteresis voltage in 2D MoS2 transistors. It was found that high temperature (175 degrees C) annealing in air could increase the hysteresis voltage from 8.0 V (original device) to 28.4 V, while a next vacuum annealing would reduce the hysteresis voltage to be only 2.0 V. An energyband diagram model based on electron trapping/detrapping due to oxygen adsorption is proposed to understand the hysteresis mechanism in multilayer MoS2 FET. This simple method for tuning the hysteresis voltage of MoS2 FET can make a significant step toward 2D nanoelectronic device applications. (C) 2016 Elsevier B.V. All rights reserved.
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页码:76 / 81
页数:6
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