A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

被引：30

作者：

Yan, WST ^{[1
]}

Luong, HC ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Dept Elect & Elect Engn, Kowloon, Hong Kong, Peoples R China

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 02期

关键词：

frequency synthesis; frequency synthesizer; phase-locked loop; radio frequency; voltage-controlled oscillator;

D O I：

10.1109/4.902761

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 900-MHz monolithic CMOS dual-loop frequency Synthesizer suitable for GSM receivers is presented. Implemented in a 0.5-mum CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm(2) and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.

引用

页码：204 / 216

页数：13

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