A CMOS Wideband Current-Mode Digital Polar Power Amplifier With Built-In AM-PM Distortion Self-Compensation

被引:40
作者
Park, Jong Seok [1 ]
Wang, Yanjie [2 ]
Pellerano, Stefano [2 ]
Hull, Christopher [2 ]
Wang, Hua [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30308 USA
[2] Intel Corp, Hillsboro, OR 97124 USA
关键词
CMOS; linearity; orthogonal frequency-division multiplexing (OFDM); phase distortion; power amplifiers (PAs); transformer; wideband; LP CMOS; NM CMOS; TRANSFORMER; TRANSMITTER; LOOP; PA; PREDISTORTION; LINEARIZATION; DESIGN; RANGE;
D O I
10.1109/JSSC.2017.2760898
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a fully integrated wideband current-mode digital polar power amplifier (DPA) in CMOS with built-in AM-PM distortion self-compensation. Feedforward capacitors are implemented in each differential cascode digital power cell. These feedforward capacitors operate together with a proposed DPA biasing scheme to minimize the DPA output device capacitance C-d variations over a wide output power range and a wide carrier frequency bandwidth, resulting in DPA AM-PM distortion reduction. A three-coil transformer-based DPA output passive network is implemented within a single transformer footprint (330 mu m x 330 mu m) and provides parallel power combining and load impedance transformation with a low loss, an octave bandwidth, and a large impedance transformation ratio. Moreover, this proposed power amplifier (PA) output passive network shows a desensitized phase response to C-d variations and further suppresses the DPA AM-PM distortion. Both proposed AM-PM distortion self-compensation techniques are effective for a large carrier frequency range and a wide modulation bandwidth, and are independent of the DPA AM control codes. This results in a superior inherent DPA phase linearity and reduces or even eliminates the need for phase pre-distortion, which dramatically simplifies the DPA pre-distortion computations. As a proof-of-concept, a 2-4.3 GHz wideband DPA is implemented in a standard 28-nm bulk CMOS process. Operating with a low supply voltage of 1.4 V for enhanced reliability, the DPA demonstrates +/- 0.5 dB PA output power bandwidth from 2 to 4.3 GHz with +24.9 dBm peak output power at 3.1 GHz. The measured peak PA drain efficiency is 42.7% at 2.5 GHz and is more than 27% from 2 to 4.3 GHz. The measured PA AM-PM distortion is within 6.8 degrees at 2.8 GHz over the PA output power dynamic range of 25 dB, achieving the lowest AM-PM distortion among recently reported current-mode DPAs in the same frequency range. Without any phase pre-distortion, modulation measurements with a 20-MHz 802.11n standard compliant signal demonstrate 2.95% rms error vector magnitude, -33.5 dBc adjacent channel leakage ratio, 15.6% PA drain efficiency, and +14.6 dBm PA average output power at 2.8 GHz.
引用
收藏
页码:340 / 356
页数:17
相关论文
共 71 条
  • [1] Monolithic Power-Combining Techniques for Watt-Level 2.4-GHz CMOS Power Amplifiers for WLAN Applications
    Afsahi, Ali
    Larson, Lawrence E.
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2013, 61 (03) : 1247 - 1260
  • [2] Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 x 2 802.11n MIMO WLAN SoC
    Afsahi, Ali
    Behzad, Arya
    Magoon, Vikram
    Larson, Lawrence E.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (05) : 955 - 966
  • [3] Distributed active transformer - A new power-combining and impedance-transformation technique
    Aoki, I
    Kee, SD
    Rutledge, DB
    Hajimiri, A
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2002, 50 (01) : 316 - 331
  • [4] A Fully Integrated, Regulatorless CMOS Power Amplifier for Long-Range Wireless Sensor Communication
    Bhagavatula, Venumadhav
    Wesson, William C.
    Shin, Soon-Kyun
    Rudell, Jacques C.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (05) : 1225 - 1236
  • [5] Bhat R, 2017, ISSCC DIG TECH PAP I, P234, DOI 10.1109/ISSCC.2017.7870347
  • [6] Bhat R, 2014, IEEE RAD FREQ INTEGR, P413, DOI 10.1109/RFIC.2014.6851755
  • [7] Chee YH, 2017, ISSCC DIG TECH PAP I, P292, DOI 10.1109/ISSCC.2017.7870376
  • [8] A Digitally Intensive Transmitter/PA Using RF-PWM With Carrier Switching in 130 nm CMOS
    Cho, Kunhee
    Gharpurey, Ranjit
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (05) : 1188 - 1199
  • [9] Chowdhury Debopriyo, 2009, 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009), P378, DOI 10.1109/ISSCC.2009.4977466
  • [10] An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology
    Chowdhury, Debopriyo
    Ye, Lu
    Alon, Elad
    Niknejad, Ali M.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (08) : 1796 - 1809