A Low-Power Single-Phase Clock Multiband Flexible Divider

被引：35

作者：

Manthena, Vamshi Krishna ^{[1
]}

Manh Anh Do ^{[1
]}

Boon, Chirn Chye ^{[1
]}

Yeo, Kiat Seng ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2012年 / 20卷 / 02期

关键词：

DFF; dual modulus prescaler; dynamic logic; E-TSPC; frequency synthesizer; high-speed digital circuits; true single-phase clock (TSPC); wireless LAN (WLAN); CMOS FREQUENCY-SYNTHESIZER;

D O I：

10.1109/TVLSI.2010.2100052

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-mu m CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.

引用

页码：376 / 380

页数：5

共 13 条

[1]

Alioto M., 2005, MODEL DESIGN BIPOLAR

[2] A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors [J].

Deng, Ping-Yuan ;

Kiang, Jean-Fu .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (02) :320-326

[3]

Ji-ren Y., 1989, IEEE J SOLID-ST CIRC, V24, P62

[4] A low power fully programmable 1MHz resolution 2.4GHz CMOS PLL frequency synthesizer [J].

Krishna, M. Vamshi ;

Xie, J. ;

Lim, W. M. ;

Do, M. A. ;

Yeo, K. S. ;

Boon, C. C. .

2007 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE, 2007, :187-190

[5] A 1.8-V 6.5-GHz Low Power Wide Band Single-Phase Clock CMOS 2/3 Prescaler [J].

Krishna, M. Vamshi ;

Boon, C. C. ;

Yeo, K. S. ;

Lim, Wei Meng .

53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, :149-152

[6] A 1-V 9.7-mW CMOS frequency synthesizer for IEEE 802. 11a transceivers [J].

Leung, Lincoln Lai Kan ;

Luong, Howard C. .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2008, 56 (01) :39-48

[7] A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider [J].

Pellerano, S ;

Levantino, S ;

Samori, C ;

Lacaita, AL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (02) :378-383

[8]

RaBaey J.M, 2003, ELECT VLSI

[9] A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver [J].

Rategh, HR ;

Samavati, H ;

Lee, TH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (05) :780-787

[10] 4.2mW CMOS frequency synthesizer for 2.4GHz ZigBee application with fast settling time performance [J].

Shin, Sangho ;

Lee, Kwyro ;

Kang, Sung-Mo .

2006 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-5, 2006, :411-+

← 1 2 →