共 50 条
- [2] Characterization and modeling of multiple coupled on-chip interconnects on silicon substrate ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2000, : 333 - 336
- [3] Equivalent circuit modeling of single and coupled on-chip interconnects on lossy silicon substrate IEEE Top Meet Ekectr Perform Electron Packag, (185-188):
- [4] Characterization and Modeling of CMOS on-chip coupled interconnects ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 159 - +
- [5] Wideband Lumped Element Model for On-Chip (A)symmetrical Coupled Interconnects on Lossy Silicon Substrate 2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5, 2007, : 2301 - 2304
- [7] Reduced order modeling of coupled on-chip interconnects for silicon-based RF integrated circuits 2000 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3, 2000, : 973 - 976
- [8] Reduced order modeling of coupled on-chip interconnects for silicon-based RF integrated circuits IEEE MTT-S International Microwave Symposium Digest, 2000, 2 : 973 - 976
- [9] Wideband lumped element model for on-chip interconnects on lossy silicon substrate 2006 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2006, : 529 - +
- [10] Inductance Modeling for On-Chip Interconnects Analog Integrated Circuits and Signal Processing, 2003, 35 : 65 - 78