High Performance VLSI Implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 Encoder

被引：0

作者：

Mukherjee, R. ^{[1
]}

Mahajan, V. ^{[1
]}

Chakrabarti, I. ^{[1
]}

Sengupta, S. ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

2013 FOURTH NATIONAL CONFERENCE ON COMPUTER VISION, PATTERN RECOGNITION, IMAGE PROCESSING AND GRAPHICS (NCVPRIPG) | 2013年

关键词：

VLSI; CAVLC; H.264; FPGA; LUT;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The video coding standard H.264 uses Contextbased Adaptive Variable Length Coding (CAVLC) as one of its entropy encoding techniques. This paper proposes VLSI architecture for CAVLC algorithm. The designed hardware meets the required speed of H.264 without compromising the hardware cost. The CAVLC encoder works at a maximum clock frequency of 126 MHz when implemented in Xilinx 10.1i, Virtex-5 technology. The speed is quite appreciable when compared to other existing works. The implemented architecture meets the required rate for processing of HD-1080 format video sequence.

引用

页数：4

共 9 条

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