3D Integration Technology using Hybrid Wafer Bonding and Via-last TSV Process

被引：0

作者：

Takeda, Kenichi ^{[1
]}

Aoki, Mayu ^{[1
]}

机构：

[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan

来源：

2014 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC) | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A three-layer-stacked wafer with CMOS devices was fabricated by using hybrid wafer bonding and backside-via-last TSV (7-mu m diameter/25-mu m length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings seamless copper bonding in face-to-face (F2F) and back-to-face (B2F) configurations. The low capacitance of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 mu m from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV.

引用

页码：211 / 213

页数：3