A 2.8-4.3GHz Wideband Fractional-N Sub-sampling Synthesizer with-112.5dBc/Hz In-Band Phase Noise

被引：0

作者：

Bajestan, Masoud Moslehi ^{[1
]}

Attah, Hubert ^{[1
]}

Entesari, Kamran ^{[1
]}

机构：

[1] Texas A&M Univ, AMSC, College Stn, TX 77843 USA

来源：

2016 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2016年

关键词：

Fractional-N synthesizer; low jitter; low phase noise; phase-locked-loop (PLL); sub-sampling PLL; wideband; PLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.8-4.3GHz low noise fractional-N subsampling frequency synthesizer in 40nm CMOS technology is presented in this paper. The reference sampling clock is modulated by a 10-bit edge modulator to achieve fractional phase lock. A novel fast two-step background calibration is used to correct gain errors in the edge modulator, reducing fractional spurs. For a 3.75GHz carrier, the synthesizer achieves 376fs rms jitter with a worst case fractional spur of -48.3dBc. The in-band phase noise at 200kHz offset is -112.5dBc/Hz. The system consumes a total power of 9.18mW from a 1.1V supply and occupies an area of 0.41mm(2).

引用

页码：126 / 129

页数：4

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