A 0.063 μm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

被引：69

作者：

Basker, V. S. ^{[1
,3
]}

Standaert, T. ^{[1
,3
]}

Kawasaki, H. ^{[5
]}

Yeh, C. -C. ^{[1
,3
]}

Maitra, K. ^{[4
]}

Yamashita, T. ^{[1
,3
]}

Faltermeier, J. ^{[1
,3
]}

Adhikari, H. ^{[4
]}

Jagannathan, H. ^{[1
,3
]}

Wang, J. ^{[1
,3
]}

Sunamura, H. ^{[6
]}

Kanakasabapathy, S. ^{[1
,3
]}

Schmitz, S. ^{[1
,3
]}

Cummings, J. ^{[1
,3
]}

Inada, A. ^{[6
]}

Lin, C. -H. ^{[1
,3
]}

Kulkarni, P. ^{[1
,3
]}

Zhu, Y. ^{[2
]}

Kuss, J. ^{[1
,3
]}

Yamamoto, T. ^{[6
]}

Kumar, A. ^{[2
]}

Wahl, J. ^{[4
]}

Yagishita, A. ^{[5
]}

Edge, L. F. ^{[1
,3
]}

Kim, R. H. ^{[4
]}

Mclellan, E. ^{[1
,3
]}

Holmes, S. J. ^{[1
,3
]}

Johnson, R. C. ^{[1
,3
]}

Levin, T. ^{[1
,3
]}

Demarest, J. ^{[1
,3
]}

Hane, M. ^{[6
]}

Takayanagi, M. ^{[5
]}

Colburn, M. ^{[1
,3
]}

Paruchuri, V. K. ^{[1
,3
]}

Miller, R. J. ^{[4
]}

Bu, H. ^{[1
,3
]}

Doris, B. ^{[1
,3
]}

McHerron, D. ^{[1
,3
]}

Leobandung, E. ^{[1
,3
]}

O'Neill, J. ^{[1
,3
]}

机构：

[1] Albany Nano Tech, Albany, NY 12203 USA

[2] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

[3] IBM Res, Yorktown Hts, NY 10598 USA

[4] GLOBALFOUNDRIES Inc, Santa Clara, CA USA

[5] Toshiba America Electron Components Inc, Irvine, CA USA

[6] NEC Elect, Tokyo, Japan

来源：

2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

D O I：

10.1109/VLSIT.2010.5556135

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate the smallest FinFET SRAM cell size of 0.063 mu m(2) reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

引用

页码：19 / +

页数：2

共 4 条

[1]

Guillorna M. A., 2009, IEDM, P961

[2] Silicon CMOS devices beyond scaling [J].

Haensch, W. ;

Nowak, E. J. ;

Dennard, R. H. ;

Solomon, P. M. ;

Bryant, A. ;

Dokumaci, O. H. ;

Kumar, A. ;

Wang, X. ;

Johnson, J. B. ;

Fischetti, M. V. .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2006, 50 (4-5) :339-361

[3]

Haran BS, 2008, INT EL DEVICES MEET, P625, DOI 10.1109/IEDM.2008.4796769

[4]

Kavalieros J., 2006, VLSI TECH DIGEST, P50, DOI [DOI 10.1109/VLSIT.2006.1705211, 10.1109/VLSIT.2006.1705211]

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