1-V 9-bit pipelined switched-opamp ADC

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-mum CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dS SNDR at 5-MHz clock rate, iis the supply voltage is raised to 1.5 V, the clock frequency call he increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW.