Study of the Effects of Parasitic Inductances and Device Capacitances on 1200 V, 35 A SiC MOSFET Based Voltage Source Inverter Design

被引:0
作者
Nayak, Parthasarathy [1 ]
Krishna, Vamshi M. [1 ]
Vasudevakrishna, K. [1 ]
Hatua, Kamalesh [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, Madras 600036, Tamil Nadu, India
来源
2014 IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, DRIVES AND ENERGY SYSTEMS (PEDES) | 2014年
关键词
Common mode noise; device characterization; double pulse test; EMI; parasitic inductance; SiC MOSFET; switching energy loss;
D O I
暂无
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
SiC MOSFET can switch five to ten times faster compared to state of the art Si IGBT. Due to that SiC MOSFET based power converter can be lighter in weight, highly efficient, compact in size compared to Si IGBT based power converters. But the parasitic inductance in the power circuit will not allow SiC MOSFET to switch to its full potential due to very high device voltage overshoot, sustained oscillation in line currents and device voltages, high EMI noise injected in the control circuit etc. Therefore it is very important to know the behavior of the switching characteristics of the device at different parasitic condition. In this paper switching behavior of a 1200V, 35 A, SiC MOSFET is tested extensively in different parasitic condition. A limiting value of these inductances is provided to build a voltage source inverter with SiC MOSFET utilizing its full switching potential.
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页数:6
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