Off State Incorporation into the 3 energy mode Device Lifetime Modeling for advanced 40nm CMOS node

被引：20

作者：

Bravaix, A. ^{[1
]}

Guerin, C. ^{[1
,3
]}

Goguenheim, D. ^{[1
]}

Huard, V. ^{[2
]}

Roy, D. ^{[2
]}

Besset, C. ^{[2
]}

Renard, S. ^{[2
]}

Randriamihaja, Y. Mamy ^{[2
]}

Vincent, E. ^{[2
]}

机构：

[1] Maison Technol, UMR CNRS 6242, ISEN IM2NP, Pl G Pompidou, F-83000 Toulon, France

[2] Crolles Alliance 2, STMicroelect, F-38926 Crolles, France

[3] Roth & Rau Switzerland AG, CH-2000 Neuchatel, Switzerland

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

Off Mode; Gate-Induced Drain Leakage; Cold Carriers; Band to Band Tunneling; Hot Carriers; Interface traps; Oxide traps; Multi Vibrational Excitation; High Temperature; HOT-CARRIER DEGRADATION; NBTI DEGRADATION; LEAKAGE CURRENT; INTERFACE; REDUCTION; GATE; MECHANISMS; TRANSISTOR; GENERATION; MOSFETS;

D O I：

10.1109/IRPS.2010.5488852

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-VT regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.

引用

页码：55 / 64

页数：10

共 45 条

[11] Device scaling limits of Si MOSFETs and their application dependencies
Frank, DJ
Dennard, RH
Nowak, E
Solomon, PM
Taur, Y
Wong, HSP
[J]. PROCEEDINGS OF THE IEEE, 2001, 89 (03) : 259 - 288
[12] GRASSER T, 2008, TUT P INT REL PHYS S, P113
[13] General framework about defect creation at the Si/SiO2 interface
Guerin, C.
Huard, V.
Bravaix, A.
[J]. JOURNAL OF APPLIED PHYSICS, 2009, 105 (11)
[14] The energy-driven hot-carrier degradation modes of nMOSFETs
Guerin, Chloe
Huard, Vincent
Bravaix, Alain
[J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2007, 7 (02) : 225 - 235
[15] High-performance chip reliability from short-time-tests - Statistical models for optical interconnect and HCI/TDDB/NBTI deep-submicron transistor failures
Haggag, A
McMahon, W
Hess, K
Cheng, K
Lee, J
Lyding, J
[J]. 39TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2001, 2001, : 271 - 279
[16] HESS K, 2000, IEDM, P10
[17] HOT-ELECTRON-INDUCED MOSFET DEGRADATION - MODEL, MONITOR, AND IMPROVEMENT
HU, CM
TAM, SC
HSU, FC
KO, PK
CHAN, TY
TERRILL, KW
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 375 - 385
[18] New characterization and modeling approach for NBTI degradation from transistor to product level
Huard, V.
Parthasarathy, C.
Rallet, N.
Guerin, C.
Mammase, M.
Barge, D.
Ouvrard, C.
[J]. 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 797 - +
[19] NBTI degradation: From physical mechanisms to modelling
Huard, V
Denais, M
Parthasarathy, C
[J]. MICROELECTRONICS RELIABILITY, 2006, 46 (01) : 1 - 23
[20] HUARD V, 2009, TUT P INT REL PHYS S, P113

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