High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree

被引：19

作者：

Chen, Yuan-Ho ^{[1
]}

Chang, Tsin-Yuan ^{[1
]}

Li, Chung-Yi ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 04期

关键词：

Distributed arithmetic (DA)-based; error-compensated adder-tree (ECAT); 2-D discrete cosine transform (DCT); DISCRETE COSINE TRANSFORM; IMPLEMENTATION; ARCHITECTURE;

D O I：

10.1109/TVLSI.2009.2037968

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with gate counts of 22.2 K for the PSNR requirements outlined in the previous works.

引用

页码：709 / 714

页数：7

共 17 条

[1] NEW SYSTOLIC ARRAY IMPLEMENTATION OF THE 2-D DISCRETE COSINE TRANSFORM AND ITS INVERSE
CHANG, YT
WANG, CL
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1995, 5 (02) : 150 - 157
[2] An area efficient high performance DCT distributed architecture for video compression
Chen, Yanling
Cao, Xixin
Xie, Qingqing
Peng, Chungan
[J]. 9TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY: TOWARD NETWORK INNOVATION BEYOND EVOLUTION, VOLS 1-3, 2007, : 238 - +
[3] Design of low-error fixed-width modified booth multiplier
Cho, KJ
Lee, KC
Chung, JG
Parhi, KK
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (05) : 522 - 531
[4] Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic
Ghosh, S
Venigalla, S
Bayoumi, M
[J]. IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN, 2005, : 162 - 166
[5] A high-speed 2-D transform architecture with unique kernel for multi-standard video applications
Huang, Chong-Yu
Chen, Lien-Fei
Lai, Yeong-Kang
[J]. PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 21 - 24
[6] Area-efficient multipliers for digital signal processing applications
Kidambi, SS
ElGuibaly, F
Antoniou, A
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1996, 43 (02): : 90 - 95
[7] Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor
Lin, Chin-Teng
Yu, Yuan-Chu
Van, Lan-Da
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (08) : 1058 - 1071
[8] Unified systolic-Like architecture for DCT and DST using distributed arithmetic
Meher, Pramod Kumar
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2006, 53 (12) : 2656 - 2663
[9] PENG C, 2007, P INT C ASIC, P189
[10] RIZK MRM, 2007, P INT DES TEST WORKS, P120

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