Circuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface

被引：0

作者：

Okada, Akira ^{[1
]}

Junaidi, Abdul Raziz ^{[1
]}

Take, Yasuhiro ^{[1
]}

Kosuge, Atsutake ^{[1
]}

Kuroda, Tadahiro ^{[1
]}

机构：

[1] Keio Univ, Yokohama, Kanagawa, Japan

来源：

2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP integration. It utilizes the advantages of both TSV and LPDDR by using a ThruChip Interface (TCI) and an ultra-thin fan-out wafer level package (UT-FOWLP). The TCI allows data communication between the stacked chips while the UT-FOWLP thins the chips stacking distance and provides the chips with power. This proposed DRAM/SoC interface outperforms WIO2 with TSV in terms of area efficiency (4x better), immunity from simultaneous switching output (SSO) noise (32x better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness. The inductive-coupling interface is newly designed to allow 12x improvement on its area efficiency. By using overlapping coils with quadrature phase division multiplexing (PDM), the coil density is increased by 4 times. The coil density is further increased by 3 times by shortening communication distance with the UT-FOWLP.

引用

页码：44 / 45

页数：2