A Low-Power High-Input-Impedance ECG Readout System Employing a Very High-Gain Amplification and a Signal-Folding Technique for Dry-Electrode Recording

This paper presents the design of a low-power electrocardiogram (ECG) readout system suitable for use in recording ECG from dry electrodes. To minimize the system's overall power consumption, we employ a very high gain (69 dB) along with a discrete-time signal-folding technique to prevent signal saturation in the amplification stage to reduce the required resolution of the analog-to-digital converter (ADC) to only 8 bits. Fabricated in a standard 0.18-mu m CMOS process with an active area of 1.07 mm(2), the proposed readout system exhibits an input impedance exceeding 1 G Omega in a bandwidth of 0.5-150 Hz, an overall input-referred noise of 2.9 mu V-rms, an input range of 12.5 mVpp, while consuming a total current of 4.5 mu A from a 1.2-V supply voltage.