Modified Cascaded Multi-level Inverter Structure with Reduced Voltage Stress Across H-Bridge for High Voltage Application

被引：1

作者：

Choudhary, Rahul ^{[1
]}

Suryawanshi, Hiralal M. ^{[1
]}

Talapur, Girish G. ^{[1
]}

Chaudhari, Madhuri A. ^{[1
]}

Shitole, Amardeep Balasaheb ^{[1
]}

机构：

[1] Visvesvaraya Natl Inst Technol, Dept Elect Engn, Nagpur, Maharashtra, India

来源：

ELECTRIC POWER COMPONENTS AND SYSTEMS | 2018年 / 46卷 / 06期

关键词：

high voltage application; level shift PWM; multi-band hysteresis current control; multi-level inverter; reduced switch multi-level topology; CONVERTER; TOPOLOGIES; OPERATION;

D O I：

10.1080/15325008.2018.1466007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a modified cascaded multi-level structure for high voltage application. The topology proposed optimizes switch count per voltage level along with the reduction in voltage stress across the switches. Optimization based on different criteria has been discussed and a comparison of the proposed structure with existing topology has been carried out. This paper also shows a level shift PWM control scheme and a closed loop multi-band hysteresis control scheme. The topology is simulated for the above two control schemes on MATLAB and also verified experimentally for single phase seven-level inverter. The experimental verification was done with DSP F28337D TI Launchpad on series resistance and inductance (RL) load.

引用

页码：659 / 672

页数：14

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