Modified Cascaded Multi-level Inverter Structure with Reduced Voltage Stress Across H-Bridge for High Voltage Application

This paper presents a modified cascaded multi-level structure for high voltage application. The topology proposed optimizes switch count per voltage level along with the reduction in voltage stress across the switches. Optimization based on different criteria has been discussed and a comparison of the proposed structure with existing topology has been carried out. This paper also shows a level shift PWM control scheme and a closed loop multi-band hysteresis control scheme. The topology is simulated for the above two control schemes on MATLAB and also verified experimentally for single phase seven-level inverter. The experimental verification was done with DSP F28337D TI Launchpad on series resistance and inductance (RL) load.