A New FVF and QFGMOS Based High-Performance Low Voltage Analog Squarer-Divider Circuit

Squarer-divider (SD) is a basic circuit that is used as a fundamental component in designing of various mathematical circuits. A high-performance SD circuit can be designed using MOS translinear loop (MTL) with transistors operating in strong inversion region. In this paper, a simple high-performance SD circuit operating at very low voltage of 0.7 V has been designed by MTL transistors biased using flipped voltage follower (FVF) cell. The FVF cell helps in reducing the voltage headroom consumption of stacked MOSFETs and thereby reduces overall supply voltage requirement of the circuit. It offers a bandwidth (BW) of 44.24 MHz and output resistance (r(out)) of 6.9K omega when simulated in Cadence Virtuoso environment using 0.18 mu m GPDK technology file. Further in the paper, another low voltage SD circuit (SD-II) has been proposed that offers higher BW and r(out). These characteristics have been achieved by replacing floating-gate MOSFETs of original SD circuit with quasi-floating gate MOSFETs. Proposed SD-II shows an improvement in BW and r(out) by a factor of 1.2 and 1.31, respectively. Additional enhancement in BW is observed by the use of a compensating resistor between gate terminals of MOSFETs forming current mirror at output side (SD-III). To show the robustness of proposed SD-III in complete design space and with variations in temperature, corner and temperature analyses have been carried out. Application of proposed SD-III in implementing a low voltage RMS-to-DC converter operating at 0.7 V has been presented to show the practical usability of the proposed circuits.