WASP: a web-based simulator for an educational pipelined processor

This paper presents a web-based simulator for an educational pipelined RISC processor, developed at the Faculty of Electrical Engineering, University of Belgrade. The architecture and organisation of the processor are devised to include typical features of both the RISC architecture and the pipelined organisation. Its graphical simulator makes it possible to follow parts of the processor organisation at both the global level and the register transfer level. The simulator, also, enables the navigation through all parts of the processor, the customisable notifications of significant events during the execution of an instruction and the tracking of relevant values of signals and contents of registers and memory locations. The execution of instructions can be carried out forward one clock or the whole programme and can be returned one clock backward. The simulator is aimed to be used both for exercises in a laboratory and individual student training via the Internet.