A 3.2 Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance

A hybrid CDR is presented that embeds a 5 x blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual jitter tolerances. In this implementation, the jitter tolerance of a phase-tracking CDR alone is increased by a factor of 32 at frequencies below its loop filter's bandwidth, while maintaining the high-frequency jitter tolerance of a 5 x blind-oversampling CDR. Measured data from a 0.11 mu m CMOS test chip at 2.4 Gb/s confirm a 200 UI peak-to-peak jitter tolerance for a 200 kHz jitter. The test chip operates from 1.9 Gb/s to 3.5 Gb/s with a BER less than 10(-11), consuming 115 mW at 2.4 Gb/s.