A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

被引:20
|
作者
Lu, Bin [1 ]
Lu, Hongliang [1 ]
Zhang, Yuming [1 ]
Zhang, Yimen [1 ]
Cui, Xiaoran [1 ]
Lv, Zhijun [1 ]
Yang, Shizheng [1 ]
Liu, Chen [1 ]
机构
[1] Xidian Univ, Sch Microelect, State Key Lab Wide Bandgap Semicond Technol, Xian 710071, Shaanxi, Peoples R China
关键词
Capacitance model; source depletion length; terminal charges; tunnel field-effect transistor (TFET); FIELD-EFFECT TRANSISTORS; THRESHOLD VOLTAGE; DRAIN CURRENT; N TFET; SI;
D O I
10.1109/TED.2017.2775341
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.
引用
收藏
页码:299 / 307
页数:9
相关论文
共 50 条
  • [1] An analytical charge-based capacitance model for double-gate tunnel FETs
    Gholizadeh, Mahdi
    Zare, Malihe
    Hosseini, Seyed Ebrahim
    SUPERLATTICES AND MICROSTRUCTURES, 2021, 152
  • [2] A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET
    Kaur, Sarabjeet
    Raman, Ashish
    Sarin, Rakesh Kumar
    SUPERLATTICES AND MICROSTRUCTURES, 2021, 150
  • [3] An Analytical Charge Model for Double-Gate Tunnel FETs
    Zhang, Lining
    Lin, Xinnan
    He, Jin
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (12) : 3217 - 3223
  • [4] Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion
    Jazaeri, Farzan
    Barbut, Lucian
    Sallese, Jean-Michel
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (10) : 3553 - 3557
  • [5] A closed-form capacitance model for tunnel FETs with explicit surface potential solutions
    Wang, Jiaxin
    Wu, Chunlei
    Huang, Qianqian
    Wang, Chao
    Huang, Ru
    JOURNAL OF APPLIED PHYSICS, 2014, 116 (09)
  • [6] A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFET
    Roy, AS
    Sallese, JM
    Enz, CC
    SOLID-STATE ELECTRONICS, 2006, 50 (04) : 687 - 693
  • [7] A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFET
    Roy, AS
    Sallese, JM
    Enz, CC
    PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 149 - 152
  • [8] Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect
    Rassekh, Amin
    Sallese, Jean-Michel
    Jazaeri, Farzan
    Fathipour, Morteza
    Ionescu, Adrian M.
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2020, 8 : 939 - 947
  • [9] A Compact Model for Double-Gate Heterojunction Tunnel FETs
    Dong, Yunpeng
    Zhang, Lining
    Li, Xiangbin
    Lin, Xinnan
    Chan, Mansun
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (11) : 4506 - 4513
  • [10] Charge-based analytical current model for asymmetric Double-Gate MOSFETs
    Park, JS
    Lee, S
    Jhee, Y
    Shin, H
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2005, 47 : S392 - S396