Implementing a Ternary Inverter Using Dual-Pocket Tunnel Field-Effect Transistors

被引：13

作者：

Gupta, Abhinav ^{[1
]}

Saurabh, Sneh ^{[1
]}

机构：

[1] Indraprastha Inst Informat Technol, Dept Elect & Commun Engn, New Delhi 110020, India

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2021年 / 68卷 / 10期

关键词：

Inverters; Tunneling; Logic gates; TFETs; Doping; Photonic band gap; Silicon germanium; Band to band tunneling (BTBT); subthreshold swing (SS); ternary inverter; tunnel FET (TFET); AMBIPOLAR CURRENT; DESIGN; CMOS; FETS; ENHANCEMENT;

D O I：

10.1109/TED.2021.3106618

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, we propose a standard ternary inverter (STI) based on a dual-pocket tunnel FET (DP-TFET) for low-power applications. Using 2-D device simulations, we demonstrate that if appropriate doping concentration and length are chosen for the dual-pocket, then the device can exhibit ternary inverter voltage transfer characteristics (VTCs) with three stable output voltage levels. Ternary inverter characteristics are obtained by two tunneling mechanisms in the device: 1) gate bias-independent within-channel tunneling and 2) gate bias-dependent source-channel tunneling. We also demonstrate that the ternary inverter obtained could be operated at different supply voltages by controlling the pocket doping concentration.

引用

页码：5305 / 5310

页数：6

共 37 条

[1] Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain [J].

Abdi, Dawit B. ;

Kumar, M. Jagadesh .

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2014, 2 (06) :187-190

[2] Few-layer Phosphorene: An Ideal 2D Material For Tunnel Transistors [J].

Ameen, Tarek A. ;

Ilatikhameneh, Hesameddin ;

Klimeck, Gerhard ;

Rahman, Rajib .

SCIENTIFIC REPORTS, 2016, 6

[3]

[Anonymous], neuromorphic computing and neural networks in hardware

[4] LOW POWER DISSIPATION MOS TERNARY LOGIC FAMILY. [J].

Balla, Prabhakara C. ;

Antoniou, Andreas .

IEEE Journal of Solid-State Circuits, 1984, SC-19 (05) :739-749

[5]

Bohr Mark, 2007, IEEE Solid-State Circuits Society Newsletter, V12, P11, DOI [DOI 10.1109/N-SSC.2007.4785534, 10.1109/N-SSC.2007.4785534]

[6] Double-gate tunnel FET with high-κ gate dielectric [J].

Boucart, Kathy ;

Mihai Ionescu, Adrian .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733

[7] Thickness Engineered Tunnel Field-Effect Transistors Based on Phosphorene [J].

Chen, Fan W. ;

Ilatikhameneh, Hesameddin ;

Ameen, Tarek A. ;

Klimeck, Gerhard ;

Rahman, Rajib .

IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) :130-133

[8] Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].

Choi, Woo Young ;

Park, Byung-Gook ;

Lee, Jong Duk ;

Liu, Tsu-Jae King .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745

[9] SUBTHRESHOLD SLOPE OF THIN-FILM SOI MOSFETS [J].

COLINGE, JP .

IEEE ELECTRON DEVICE LETTERS, 1986, 7 (04) :244-246

[10] DARK SILICON AND THE END OF MULTICORE SCALING [J].

Esmaeilzadeh, Hadi ;

Blem, Emily ;

St Amant, Renee ;

Sankaralingam, Karthikeyan ;

Burger, Doug .

IEEE MICRO, 2012, 32 (03) :122-134

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