Implementation of Turbo Decoder Using MAX-LOG-MAP Algorithm in VHDL

被引：0
|
作者：
Mishra, Shivshankar [1 ]
Shukla, Harshit [2 ]
Madhekar, Suneel [1 ]
机构：
[1] DRDO, Res Ctr Imarat, PGAD, Hyderabad 50058, Andhra Pradesh, India
[2] PDPM IIITDM, Elect & Commun Engn Dept, Jabalpur 482005, India
来源：
2015 ANNUAL IEEE INDIA CONFERENCE (INDICON) | 2015年
关键词：
Error correcting codes; Turbo codes; iterative decoding; FPGA; MAX-LOG-MAP algorithm; INTERLEAVER DESIGN; CODES;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With the advent of FPGAs, the realization of the BCJR algorithm and different simplified versions of BCJR algorithm on hardware is possible. A VHDL implementation of Turbo decoder using the MAX-LOG-MAP algorithm has been discussed in this paper. The target device used for this implementation is Xilinx Virtex-6 FPGA. Simulation and synthesis were carried out using ModelSim SE 6.1 and Xilinx ISE 10.1. BER plots and input and output waveforms for interleaver, deinterleaver, MAX-LOG-MAP decoder and Turbo decoder are also presented.
引用
收藏
页数：6
相关论文
共 50 条
  • [41] 基于Turbo码的Max-Log-MAP译码算法的改进
    汪汉新
    叶俊民
    现代电子技术, 2003, (16) : 37 - 39
  • [42] A comparative study on the modified Max-Log-MAP turbo decoding by extrinsic information scaling
    Taskaldiran, Mustafa
    Morling, Richard C. S.
    Kale, Izzet
    2007 WIRELESS TELECOMMUNICATIONS SYMPOSIUM, 2007, : 7 - 11
  • [43] Decoding of product codes use of annealed max-log-MAP algorithm
    Karami, Ebrahim
    2005 39th Asilomar Conference on Signals, Systems and Computers, Vols 1 and 2, 2005, : 415 - 416
  • [44] Reduced complexity Max-Log-MAP Sphere Decoder using Group Detection in MIMO-OFDM systems
    Aoki, T
    Tanabe, Y
    Matsuoka, H
    Shoki, H
    IEICE TRANSACTIONS ON COMMUNICATIONS, 2005, E88B (11) : 4220 - 4228
  • [45] An improved Max-Log-Map algorithm using scaling factors in 3GPP system
    School of Information Engineering, Communication University of China, Beijing , China
    Shi, Yameng, 1600, Binary Information Press (10):
  • [46] FPGA implementation of turbo decoder for WCDMA system: High efficient structure for log-MAP turbo decoder
    Jiang, Jun
    Bai, Chun-Long
    Zhang, Ping
    Hu, Jian-Dong
    Beijing Youdian Daxue Xuebao/Journal of Beijing University of Posts and Telecommunications, 2002, 25 (01): : 22 - 26
  • [47] High Speed Low Complexity Radix-16 Max-Log-MAP SISO Decoder
    Sanchez, Oscar
    Jego, Christophe
    Jezequel, Michel
    Saouter, Yannick
    2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012, : 400 - 403
  • [48] Pipeline Sliding Window Max-Log-MAP Algorithm for CPM Noncoherent Detection
    Liu, Dongpei
    Liu, Hengzhu
    Zhou, Li
    Zhang, Liyong
    PROCEEDINGS OF 2013 IEEE 4TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS), 2012, : 824 - 827
  • [49] Simplified recursive structure for turbo decoder with LOG-MAP algorithm
    Bai, CL
    Jiang, J
    Zhang, P
    IEEE 55TH VEHICULAR TECHNOLOGY CONFERENCE, VTC SPRING 2002, VOLS 1-4, PROCEEDINGS, 2002, : 1012 - 1015
  • [50] Optimizations in max-log-MAP LLRe VLSI architecture
    Pérez, JM
    Fernández, V
    ISSCS 2005: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2005, : 359 - 362
12345