The application of dry photoresists in fabricating cost-effective tapered through-silicon vias and redistribution lines in a single step

被引:9
作者
Dixit, Pradeep [1 ]
Salonen, Jaakko [1 ]
Pohjonen, Harri [1 ]
Monnoyer, Philippe [1 ]
机构
[1] VTT Tech Res Ctr Finland, Espoo 02044, Finland
关键词
HIGH-ASPECT-RATIO; COPPER ELECTRODEPOSITION; HIGH-DENSITY; MEMS; INTERCONNECTS; TECHNOLOGY;
D O I
10.1088/0960-1317/21/2/025020
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we report a simple and cost-effective technique to fabricate a partially electroplated tapered through-silicon via (TSV) and redistribution line (RDL)-like structures on the field in a single process step using dry laminated photoresists. An array of 100 mu m deep positively tapered silicon vias was etched by a three-step non-Bosch plasma etching process. Insulation, diffusion barrier and seed layers were deposited by low-temperature plasma-enhanced chemical vapor deposition and sputtering processes, respectively. A 15 mu m thick dry MXA115 photoresist was laminated on the wafer by a roller-less vacuum lamination process. The dry resist allows a satisfactory patterning of the RDL-like structures by eliminating the chances of resist residuals falling in the etched TSVs. Direct-current (dc) electroplating was used to deposit 10 mu m thick copper layers on the via sidewalls as well as on the field. Therefore, the electroplating not only partially fills the vias but also forms the RDL structures at the same time. Since both TSVs and RDLs are fabricated together in a single process step, several conventional process steps such as over-burden polishing, lithography, and metal etching were avoided. Compared to the conventional TSV fabrication processes, this dry resist lithography-based method turned out to be simple and very cost-effective in making complex TSV interconnects.
引用
收藏
页数:11
相关论文
共 31 条
[1]   Fabrication and characterization of robust through-silicon vias for silicon-carrier applications [J].
Andry, P. S. ;
Tsang, C. K. ;
Webb, B. C. ;
Sprogis, E. J. ;
Wright, S. L. ;
Dang, B. ;
Manzer, D. G. .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2008, 52 (06) :571-581
[2]   Stackable system-on-packages with integrated components [J].
Becker, KF ;
Jung, E ;
Ostmann, A ;
Braun, T ;
Neumann, A ;
Aschenbrenner, R ;
Reichl, H .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2004, 27 (02) :268-277
[3]   Through silicon via copper electrodeposition for 3D integration [J].
Beica, Rozalia ;
Sharbono, Charles ;
Ritzdorf, Tom .
58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, :577-+
[4]   Thick photoresist development for the fabrication of high aspect ratio magnetic coils [J].
Brunet, M ;
O'Donnell, T ;
O'Brien, J ;
McCloskey, P ;
O Mathuna, SC .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2002, 12 (04) :444-449
[5]   Thermo-mechanical Characterization of Copper Filled and Polymer Filled TSVs Considering Nonlinear Material Behaviors [J].
Chen, Zhaohui ;
Song, Xiaohui ;
Liu, Sheng .
2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, :1374-1380
[6]   Aspect-ratio-dependent copper electrodeposition technique for very high aspect-ratio through-hole plating [J].
Dixit, P ;
Miao, JM .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2006, 153 (06) :G552-G559
[7]   High aspect ratio vertical through-vias for 3D MEMS packaging applications by optimized three-step deep RIE [J].
Dixit, Pradeep ;
Miao, Jianmin .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2008, 155 (02) :H85-H91
[8]   Mechanical and microstructural characterization of high aspect ratio through-wafer electroplated copper interconnects [J].
Dixit, Pradeep ;
Xu, Luhua ;
Miao, Jianmin ;
Pang, John H. L. ;
Preisser, Robert .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2007, 17 (09) :1749-1757
[9]   Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating [J].
Dixit, Pradeep ;
Tan, Chee Wee ;
Xu, Luhua ;
Lin, Nay ;
Miao, Jianmin ;
Pang, John H. L. ;
Backus, Petra ;
Preisser, Robert .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2007, 17 (05) :1078-1086
[10]   Fabrication of high aspect ratio 35 μm pitch through-wafer copper interconnects by electroplating for 3-D wafer stacking [J].
Dixit, Pradeep ;
Miao, Jianmin ;
Preisser, Robert .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2006, 9 (10) :G305-G308