Advanced PBTI reliability with 0.69 nm EOT GdHfO gate dielectric

被引：3

作者：

Cho, Moonju ^{[1
]}

Aoulaiche, Marc ^{[1
]}

Degraeve, Robin ^{[1
]}

Kaczer, Ben ^{[1
]}

Kauerauf, Thomas ^{[1
]}

Ragnarsson, Lars-Ake ^{[1
]}

Adelmann, Christoph ^{[1
]}

Van Elshocht, Sven ^{[1
]}

Hoffmann, Thomas Y. ^{[1
]}

Groeseneken, Guido ^{[1
,2
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, ESAT Dept, Louvain, Belgium

来源：

SOLID-STATE ELECTRONICS | 2011年 / 63卷 / 01期

关键词：

PBTI; Thin EOT; Dielectric reliability; SILC; HIGH-K;

D O I：

10.1016/j.sse.2011.06.001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The reliability of 0.69 nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78 nm EOT HfO2 + La2O3 (or HfLaO) device. The resulting reliable gate over-drive at 10 years of this GdHfO device is 0.85 V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device. (C) 2011 Elsevier Ltd. All rights reserved.

引用

页码：5 / 7

页数：3

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